EdgeAI aims at the widespread deployment of AI on edge devices. Given the estimated one trillion IoT devices expected by 2035, such a rapid growth necessitates new breakthroughs in machine learning (ML) in order to fully exploit the compute power of these devices. Indeed, a critical requirement of future ML systems is to enable on-device automated training and inference in distributed settings, where and when data, devices, or users are present, without sending training (possibly sensitive) data to the cloud or incurring long response times. For example, with suitable ML models and hardware support, a network of autonomous vehicles or AR/VR devices can enable on-device ML-based video/image processing, as well as quickly re-train models to adapt to new data.

Starting from these overarching considerations, we focus on three major challenges to rapid adoption of deep learning at the edge, namely response time and energy efficiency, data privacy, and network-awareness of distributed deep learning. Furthermore, we consider on-device distributed learning, the hardware it runs on, and their co-design to allow efficient distribution of ML tasks across the IoT hierarchy, federated learning among edge nodes, and resource-aware ML deployment on edge devices. We hope to convey the excitement of working in this problem space that brings together topics in ML, optimization, communications, and application-hardware (co-)design.

Radu Marculescu is a Professor and the Laura Jennings Turner Chair in Engineering in the Department of Electrical and Computer Engineering at The University of Texas at Austin. Between 2000-2019, he was a Professor in the Electrical and Computer Engineering department at Carnegie Mellon University. His current research focuses on developing ML/AI methods and tools for modeling, analysis, and optimization of embedded systems, cyber-physical systems, social networks, and Internet-of-Things. He has received the 2019 IEEE Computer Society Edward J. McCluskey Technical Achievement Award, for seminal contributions to the science of network on chip design, analysis, and optimization. Most recently, he received the 2020 ESWEEK Test-of-Time Award from The International Conference on Hardware/Software Co-Design and System Synthesis (CODES). He is a Fellow of the IEEE.